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| DATA SHEET MOS INTEGRATED CIRCUIT PD75P3018A 4-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The PD75P3018A replaces the PD753017A's internal mask ROM with a one-time PROM, and features expanded ROM capacity. The PD75P3018A inherits the function of the PD75P3018, and enables high-speed operation at a low supply voltage of 1.8 V. Because the PD75P3018A supports programming by users, it is suitable for use in evaluation of systems in development stages using the PD753012A, 753016A, or 753017A, and for use in small-scale production. The following document describes further details of the functions. Please make sure to read this document before starting design. PD753017 User's Manual : U11282E FEATURES Compatible with PD753017A Memory capacity: * PROM : 32768 x 8 bits * RAM : 1024 x 4 bits Can operate in the same power supply voltage as the mask version PD753017A * VDD = 1.8 to 5.5 V LCD controller/driver ORDERING INFORMATION Part Number Package 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.05 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.00 mm) PD75P3018AGC-3B9 PD75P3018AGC-8BT PD75P3018AGK-BE9 PD75P3018AGK-9EU Caution Mask-option pull-up resistors are not provided in this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U11917EJ2V0DS00 (2nd edition) Date Published July 2000 N CP (K) Printed in Japan The mark shows major revised points. (c) 1997, 2000 PD75P3018A FUNCTION OUTLINE Item Instruction execution time Function * 0.95, 1.91, 3.81, 15.3 s (main system clock: at 4.19 MHz operation) * 0.67, 1.33, 2.67, 10.7 s (main system clock: at 6.0 MHz operation) * 122 s (subsystem clock: at 32.768 kHz operation) 32768 x 8 bits 1024 x 4 bits * 4-bit operation: 8 x 4 banks * 8-bit operation: 4 x 4 banks 8 16 8 8 40 * Segment number selection : 24/28/32 segments (can be changed to CMOS output port in unit of 4; max. 8) * Display mode selection : Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias) 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) 5 channels: * 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter, carrier generator, timer with gate) * Basic interval timer/watchdog timer: 1 channel * Watch timer: 1 channel * 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit * 2-wire serial I/O mode * SBI mode 16 bits * , 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation) * , 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation) * 2, 4, 32 kHz (main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) * 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation) * External : 3 * Internal : 5 * External : 1 * Internal : 1 * Ceramic or crystal oscillator for main system clock oscillation * Crystal oscillator for subsystem clock oscillation STOP/HALT mode VDD = 1.8 to 5.5 V * 80-pin plastic QFP (14 x 14 mm) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) Also used for segment pins 13 V breakdown voltage On-chip pull-up resistor connection can be specified by using software: 23 Internal memory PROM RAM General-purpose register Input/output port CMOS input CMOS input/output CMOS output N-ch open-drain input/output Total LCD controller/driver Timer Serial interface Bit sequential buffer (BSB) Clock output (PCL) Buzzer output (BUZ) Vectored interrupt Test input System clock oscillator Standby function Power supply voltage Package 2 Data Sheet U11917EJ2V0DS00 PD75P3018A CONTENTS 1. PIN CONFIGURATION (Top View) ................................................................................................ 2. BLOCK DIAGRAM ........................................................................................................................... 3. PIN FUNCTIONS .............................................................................................................................. 3.1 3.2 3.3 3.4 Port Pins ................................................................................................................................................... Non-port Pins ........................................................................................................................................... 4 5 6 6 8 Pin Input/Output Circuits ......................................................................................................................... 10 Recommended Connection for Unused Pins ........................................................................................ 12 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ....................................... 13 4.1 4.2 Difference between Mk I Mode and Mk II Mode ..................................................................................... 13 Setting of Stack Bank Selection Register (SBS) ................................................................................... 14 5. DIFFERENCES BETWEEN PD75P3018A AND PD753012A, 753016A, AND 753017A ....... 15 6. MEMORY CONFIGURATION .......................................................................................................... 16 6.1 6.2 6.3 Program Counter (PC) ............................................................................................................................. 16 Program Memory (PROM) ....................................................................................................................... 16 Data Memory (RAM) ................................................................................................................................. 19 7. INSTRUCTION SET ......................................................................................................................... 20 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ............................................. 30 8.1 8.2 8.3 8.4 Operation Modes for Program Memory Write/Verify ............................................................................ 30 Program Memory Write Procedure ......................................................................................................... 31 Program Memory Read Procedure ......................................................................................................... 32 One-time PROM Screening ..................................................................................................................... 33 9. ELECTRICAL SPECIFICATIONS .................................................................................................... 34 10. PACKAGE DRAWINGS ................................................................................................................... 48 11. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 52 APPENDIX A. PD75316B, 753017A AND 75P3018A FUNCTION LIST .......................................... 54 APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 56 APPENDIX C. RELATED DOCUMENTS ............................................................................................... 60 Data Sheet U11917EJ2V0DS00 3 PD75P3018A 1. PIN CONFIGURATION (Top View) * 80-pin plastic QFP (14 x 14 mm) PD75P3018AGC-3B9, 75P3018AGC-8BT * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) PD75P3018AGK-BE9, 75P3018AGK-9EU S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 RESET P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P60/KR0 X2 X1 VPPNote XT2 XT1 VDD P33/MD3 P32/MD2 P31/SYNC/MD1 P30/LCDCL/MD0 P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0 P13/TI0 P12/INT2/TI1/TI2 P11/INT1 P10/INT0 P03/SI/SB1 Note Connect the VPP directly to VDD during normal operation. PIN IDENTIFICATIONS BIAS BP0-BP7 BUZ COM0-COM3 D0-D7 INT0, 1, 4 INT2 KR0-KR7 LCDCL MD0-MD3 P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 : LCD Power Supply Bias Control : Bit Port 0-7 : Buzzer Clock : Common Output 0-3 : Data Bus 0-7 : External Vectored Interrupt 0, 1, 4 : External Test Input 2 : Key Return 0-7 : LCD Clock : Mode Selection 0-3 : Port0 : Port1 : Port2 : Port3 : Port4 : Port5 : Port6 P70-P73 PCL PTO0-PTO2 RESET S0-S31 SB0, SB1 SCK SI SO SYNC TI0-TI2 VDD VLC0-VLC2 VPP Vss X1, X2 XT1, XT2 : Port7 : Programmable Clock : Programmable Timer Output 0-2 : Reset : Segment Output 0-31 : Serial Bus 0,1 : Serial Clock : Serial Input : Serial Output : LCD Synchronization : Timer Input 0-2 : Positive Power Supply : LCD Power Supply 0-2 : Programming Power Supply : Ground : Main System Clock Oscillation 1, 2 : Subsystem Clock Oscillation 1, 2 4 COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 P40/D0 P41/D1 P42/D2 P43/D3 Vss P50/D4 P51/D5 P52/D6 P53/D7 P00/INT4 P01/SCK P02/SO/SB0 Data Sheet U11917EJ2V0DS00 PD75P3018A 2. BLOCK DIAGRAM PTO1/P21 TIMER/EVENT COUNTER #1 INTT1 TIMER/EVENT COUNTER #2 INTT2 TOUT0 BASIC INTERVAL TIMER/ WATCHDOG TIMER INTBT PROGRAM COUNTER (15) ALU SP (8) CY SBS PORT0 4 P00 to P03 TI1/TI2/ P12/INT2 PORT1 4 P10 to P13 PTO2/P22/PCL PORT2 4 P20 to P23 BANK PORT3 4 P30/MD0 to P33/MD3 P40/D0 to P43/D3 P50/D4 to P53/D7 PORT4 GENERAL REG. PROM PROGRAM MEMORY 32768 x 8 BITS 4 PORT5 4 TI0/P13 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 TOUT0 DECODE AND CONTROL PORT6 RAM DATA MEMORY 1024 x 4 BITS 4 P60 to P63 BUZ/P23 WATCH TIMER INTW fLCD PORT7 4 P70 to P73 24 S0 to S23 S24/BP0 to S31/BP7 COM0 to COM3 VLC0 to VLC2 BIAS LCDCL/P30/MD0 SYNC/P31/MD1 SI/SB1/P03 SO/SB0/P02 SCK/P01 CLOCKED SERIAL INTERFACE INTCSI TOUT0 LCD CONTROLLER /DRIVER fLCD fx/2 N BIT SEQ. BUFFER (16) CPU CLOCK SYSTEM CLOCK CLOCK CLOCK GENERATOR STAND BY OUTPUT DIVIDER CONTROL CONTROL SUB MAIN PCL/PTO2/P22 XT1 XT2 X1 X2 VDD 8 INT0/P10 INT1/P11 INT2/P12/TI1/TI2 INT4/P00 KR0/P60 to KR7/P73 8 4 INTERRUPT CONTROL 3 VSS RESET VPP Data Sheet U11917EJ2V0DS00 5 PD75P3018A 3. PIN FUNCTIONS 3.1 Port Pins (1/2) Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 P40Note 2 P41Note 2 P42Note 2 P43Note 2 P50Note 2 P51Note 2 P52Note 2 P53Note 2 I/O I/O I/O I/O Input I/O Input Alternate Function INT4 SCK SO/SB0 SI/SB1 INT0 INT1 TI1/TI2/INT2 TI0 PTO0 PTO1 PCL/PTO2 BUZ LCDCL/MD0 SYNC/MD1 MD2 MD3 D0 D1 D2 D3 D4 D5 D6 D7 This is an N-ch open-drain 4-bit I/O port (PORT5). When set to open-drain, voltage is 13 V. Also functions as data I/O pin (high-order 4 bits) for program memory (PROM) write/verify. High impedance M-E This is an N-ch open-drain 4-bit I/O port (PORT4). When set to open-drain, voltage is 13 V. Also functions as data I/O pin (low-order 4 bits) for program memory (PROM) write/verify. High impedance M-E This is a programmable 4-bit I/O port (PORT3). Input and output in single-bit units can be specified. When set for 4-bit units, an internal pull-up resistor connection can be specified by software. -- Input E-B This is a 4-bit I/O port (PORT2). These are 4-bit pins for which an internal pull-up resistor connection can be specified by software. -- Input E-B This is a 4-bit input port (PORT1). These are 4-bit pins for which an internal pull-up resistor connection can be specified by software. P10/INT0 can select noise elimination circuit. -- Input Function This is a 4-bit input port (PORT0). P01 to P03 are 3-bit pins for which an internal pull-up resistor connection can be specified by software. 8-bit I/O -- After Reset I/O Circuit TypeNote 1 Input Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. Low-level input leakage current increases when input instructions or bit manipulation instructions are executed. 6 Data Sheet U11917EJ2V0DS00 PD75P3018A 3.1 Port Pins (2/2) Pin Name P60 P61 P62 P63 P70 P71 P72 P73 BP0 BP1 BP2 BP3 BP4 BP5 BP6 BP7 I/O I/O I/O Alternate Function KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 Output S24 S25 S26 S27 Output S28 S29 S30 S31 1-bit output port (BIT PORT). These pins are also used as segment output pin. -- Note 2 H-A This is a 4-bit I/O port (PORT7). When set for 4-bit units, an internal pull-up resistor connection can be specified by software. Input Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. VLC1 is selected as the input source for BP0 to BP7. The output level varies depending on the external circuit for BP0 to BP7 and VLC1. Example: As shown below, BP0 to BP7 are mutually connected via the PD75P3018A, so the output levels of BP0 to BP7 are determined by the sizes of R1, R2, and R3. VDD R2 BP0 ON VLC1 BP1 R1 ON R3 PD75P3018A Data Sheet U11917EJ2V0DS00 7 PD75P3018A 3.2 Non-port Pins (1/2) Pin Name TI0 TI1, TI2 PTO0 PTO1 PTO2 PCL BUZ SCK SO/SB0 SI/SB1 INT4 INT0 INT1 INT2 KR0-KR3 KR4-KR7 X1 X2 XT1 XT2 RESET MD0 MD1 MD2, MD3 D0-D3 D4-D7 VPP Note 2 I/O Input Alternate Function P13 P12/INT2 Function External event pulse input to timer/event counter After Reset I/O Circuit TypeNote 1 Input -C Output P20 P21 P22 P22 P23 I/O P01 P02 P03 Input Input P00 P10 P11 P12/TI1/TI2 Input Input Input -- Input -- Input Input -- P30/LCDCL P31/SYNC P32, P33 I/O P40-P43 P50-P53 -- -- -- P60-P63 P70-P73 -- Timer/event counter output Input E-B Clock output Optional frequency output (for buzzer or system clock trimming) Serial clock I/O Serial data output Serial data bus I/O Serial data input Serial data bus I/O Edge detection vectored interrupt input (both rising and falling edges detection) Edge detection vectored interrupt input Noise elimination circuit/ (detected edge is selectable) asynchronous is selectable INT0/P10 can select noise elimination circuit. Asynchronous Rising edge detection testable input Falling edge detection testable input Falling edge detection testable input Ceramic/crystal oscillation circuit connection for main system clock. If using an external clock, input to X1 and input inverted phase to X2. Crystal oscillation circuit connection for subsystem clock. If using an external clock, input to XT1 and input inverted phase to XT2. XT1 can be used as a 1-bit (test) input. System reset input (low level active) Mode selection for program memory (PROM) write/verify Asynchronous Input Input -- -- -- -- Input E-B Data bus for program memory (PROM) write/verify Input M-E Program power supply voltage for program memory (PROM) write/verify. For normal operation, connect directly to VDD. Apply +12.5 V for PROM write/verify. Positive power supply Ground -- -- VDD Vss -- -- -- -- -- -- -- -- Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. The VPP pin does not operate correctly during normal operation unless connected to the VDD pin. 8 Data Sheet U11917EJ2V0DS00 PD75P3018A 3.2 Non-port Pins (2/2) Pin Name S0-S23 S24-S31 I/O Output Alternate Function -- Segment signal output Segment signal output Common signal output Power source for LCD driver Output for external split resistor cut Clock output for driving external expansion driver Clock output for synchronization of external expansion driver Function After Reset I/O Circuit Type Note 1 Note 1 Note 1 -- High impedance Input Input G-A H-A G-B -- -- E-B E-B Output BP0-BP7 -- -- -- P30/MD0 P31/MD1 COM0-COM3 Output VLC0-VLC2 BIAS LCDCLNote 2 SYNC Note 2 -- Output I/O I/O Notes 1. The VLCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs. S0-S31: VLC1, COM0-COM2: VLC2, COM3: VLC0 2. These pins are provided for future system expansion. Currently, only P30 and P31 are used. Data Sheet U11917EJ2V0DS00 9 PD75P3018A 3.3 Pin Input/Output Circuits The input/output circuits for the PD75P3018A's pins are shown in abbreviated form below. (1/2) TYPE A VDD Data P-ch IN Output disable N-ch TYPE D VDD P-ch OUT N-ch CMOS standard input buffer Push-pull output that can be set to high impedance output (with both P-ch and N-ch OFF). TYPE E-B VDD P.U.R. P.U.R. enable P-ch TYPE B IN Data Type D Output disable IN/OUT Type A Schmitt trigger input with hysteresis characteristics. P.U.R. : Pull-Up Resistor TYPE B-C TYPE F-A VDD VDD P.U.R. P.U.R. enable P.U.R. enable Data Type D Output disable IN Type B P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor P.U.R. P-ch P-ch IN/OUT 10 Data Sheet U11917EJ2V0DS00 PD75P3018A (2/2) TYPE F-B VDD P.U.R. P.U.R. enable Output disable (P) Data Output disable Output disable (N) N-ch Bit Port data Output disable VDD P-ch IN/OUT P-ch SEG data Type G-A IN TYPE H-A Type D P.U.R. : Pull-Up Resistor TYPE G-A VLC0 VLC1 P-ch N-ch P.U.R. enable P-ch IN/OUT OUT SEG data VLC2 N-ch P.U.R. : Pull-Up Resistor N-ch Data Output disable N-ch TYPE M-C VDD P.U.R. TYPE G-B TYPE M-E IN/OUT VLC0 VLC1 P-ch N-ch Data Output disable VDD Input instruction P-ch P.U.R. Note N-ch (+13 V withstand voltage) OUT COM data N-ch P-ch VLC2 N-ch Voltage controller (+13 V withstand voltage) Note Pull-up resistor operated only when executing input instructions (when pins are low level, current flows from VDD to pins). Data Sheet U11917EJ2V0DS00 11 PD75P3018A 3.4 Recommended Connection for Unused Pins Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0, P11/INT1 P12/TI1/TI2/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PTO2/PCL P23/BUZ P30/LCDCL/MD0 P31/SYNC/MD1 P32/MD2, P33/MD3 P40/D0-P43/D3 P50/D4-P53/D7 P60/KR0-P63/KR3 P70/KR4-P73/KR7 S0-S23 S24/BP0-S31/BP7 COM0-COM3 VLC0-VLC2 BIAS XT1Note XT2 Note Recommended Connection Connect to VSS or VDD Connect to VSS or VDD via a resistor individually Connect to VSS Connect to VSS or VDD Input : Connect to VSS or VDD via a resistor individually Output : Leave open Connect to VSS Input : Connect to VSS or VDD via a resistor individually Output : Leave open Leave open Connect to VSS Connect to VSS only when VLC0 to VLC2 are all not used. In other cases, leave open. Connect to VSS Leave open Note When subsystem clock is not used, specify SOS.0 = 1 (indicates that internal feedback resistor is disconnected). 12 Data Sheet U11917EJ2V0DS00 PD75P3018A 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE Setting a stack bank selection (SBS) register for the PD75P3018A enables the program memory to be switched between Mk I mode and Mk II mode. This function is applicable when using the PD75P3018A to evaluate the PD753012A, 753016A, or 753017A. When the SBS bit 3 is set to 1 : sets Mk I mode (supports Mk I mode for PD753012A, 753016A, and 753017A) When the SBS bit 3 is set to 0 : sets Mk II mode (supports Mk II mode for PD753012A, 753016A, and 753017A) 4.1 Difference between Mk I Mode and Mk II Mode Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the PD75P3018A. Table 4-1. Difference between Mk I Mode and Mk II Mode Item Program counter Program memory (bytes) Data memory (bits) Stack Stack bank No. of stack bytes Instruction BRA !addr1 instruction CALLA !addr1 instruction Instruction CALL !addr instruction 3 machine cycles 2 machine cycles When set to Mk I mode: PD753012A, 753016A, and 753017A 4 machine cycles 3 machine cycles When set to Mk II mode: PD753012A, 753016A, and 753017A Mk I Mode PC13-0 PC14 is fixed at 0 16384 1024 x 4 Selectable via memory banks 0 to 3 2 bytes Not available 3 bytes Available PC14-0 32768 Mk II Mode execution time CALLF !faddr instruction Supported mask ROMs Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL series. Therefore, this mode is effective for enhancing software compatibility with products that have a program area of more than 16 Kbytes. With regard to the number of stack bytes during execution of subroutine call instructions, the usable area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected. However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and processing performance than on software compatibility, the Mk I mode should be used. Data Sheet U11917EJ2V0DS00 13 PD75P3018A 4.2 Setting of Stack Bank Selection Register (SBS) Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for doing this. The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be sure to initialize the stack bank selection register to 10XXBNote at the beginning of the program. When using the Mk II mode, be sure to initialize it to 00XXBNote. Note Set the desired value for XX. Figure 4-1. Format of Stack Bank Selection Register Address F84H 3 SBS3 2 SBS2 1 SBS1 0 SBS0 Symbol SBS Stack area specification 0 0 1 1 0 1 0 1 Memory bank 0 Memory bank 1 Memory bank 2 Memory bank 3 0 Be sure to set bit 2 to 0. Mode selection specification 0 1 Mk II mode Mk I mode Cautions 1. SBS3 is set to "1" after RESET input, and consequently the CPU operates in Mk I mode. When using instructions for Mk II mode, set SBS3 to "0" and set Mk II mode before using the instructions. 2. When using Mk II mode, execute a subroutine call instruction and an interrupt instruction after RESET input and after setting the stack bank selection register. 14 Data Sheet U11917EJ2V0DS00 PD75P3018A 5. DIFFERENCES BETWEEN PD75P3018A AND PD753012A, 753016A, AND 753017A The PD75P3018A replaces the internal mask ROM in the PD753012A, 753016A, and 753017A with a one-time PROM and features expanded ROM capacity. The PD75P3018A's Mk I mode supports the Mk I mode in the PD753012A, 753016A, and 753017A and the PD75P3018A's Mk II mode supports the Mk II mode in the PD753012A, 753016A, and 753017A. Table 5-1 lists differences among the PD75P3018A and the PD753012A, 753016A, and 753017A. Be sure to check the differences among these products before using them with PROMs for debugging or prototype testing of application systems or, later, when using them with a mask ROM for full-scale production. For the CPU functions and internal hardwares, refer to PD753017 User's Manual (U11282E). Table 5-1. Differences between PD75P3018A and PD753012A, 753016A, and 753017A Item Program counter Program memory (bytes) During Mk I mode During Mk II mode Data memory (x 4 bits) Mask options Pull-up resistor for PORT4 and PORT5 LCD split resistor Feedback resistor for subsystem clock Wait time during RESET Pin configuration Pin Nos. 29 to 32 Pin Nos. 34 to 37 Pin No. 50 Pin No. 51 Pin Nos. 52 and 53 Pin No. 57 Other Yes (Can be specified whether to use or not) Yes (Can be specified either 217/fX or 215/fX)Note P40 to P43 P50 to P53 P30/LCDCL P31/SYNC P32, P33 IC No (used) No (Fixed at 215/fX)Note P40/D0 to P43/D3 P50/D4 to P53/D7 P30/LCDCL/MD0 P31/SYNC/MD1 P32/MD2, P33/MD3 VPP PD753012A 14 bits Mask ROM 12288 12288 1024 PD753016A PD753017A 15 bits PD75P3018A One-time PROM 16384 16384 16384 24576 16384 32768 Yes (Can be specified whether to incorporate or not) No (Cannot incorporate) Noise resistance and noise radiation may differ due to the different circuit sizes and mask layouts. Note For 217/fX, during 6.0 MHz operation is 21.8 ms, and during 4.19 MHz operation is 31.3 ms. For 215/fX, during 6.0 MHz operation is 5.46 ms, and during 4.19 MHz operation is 7.81 ms. Caution Noise resistance and noise radiation are different in PROM and mask ROMs. In transferring to mask ROM version from the PROM version in a process between prototype development and full production, be sure to fully evaluate the mask ROM version's CS (not ES). Data Sheet U11917EJ2V0DS00 15 PD75P3018A 6. MEMORY CONFIGURATION 6.1 Program Counter (PC) ... 15 bits This is a 15-bit binary counter that stores program memory address data. Bit 15 is valid during Mk II mode. But PC14 is fixed at zero during Mk I mode, and the lower 14 bits are all valid. Figure 6-1. Configuration of Program Counter PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC Fixed at zero during Mk I mode 6.2 Program Memory (PROM) ... 32768 x 8 bits The program memory consists of 32768 x 8-bit one-time PROM. The program memory address can be selected as shown below by setting the stack bank selection (SBS) register. Mk I Mode Usable address 0000H to 3FFFH Mk II Mode 0000H to 7FFFH Figures 6-2 and 6-3 show the addressing ranges for the program memory and branch instruction and the subroutine call instruction, during Mk I and Mk II modes. 16 Data Sheet U11917EJ2V0DS00 PD75P3018A Figure 6-2. Program Memory Map (Mk I mode) 7 0000H MBE 6 RBE 5 0 Internal reset start address (high-order 6 bits) Internal reset start address (low-order 8 bits) 0002H MBE RBE INTBT/INT4 start address (high-order 6 bits) INTBT/INT4 start address (low-order 8 bits) CALLF !faddr instruction entry address 0004H MBE RBE INT0 start address (high-order 6 bits) INT0 start address (low-order 8 bits) 0006H MBE RBE INT1 start address (high-order 6 bits) INT1 start address (low-order 8 bits) BRCB !caddr instruction branch address 0008H MBE RBE INTCSI start address (high-order 6 bits) INTCSI start address (low-order 8 bits) 000AH MBE RBE INTT0 start address (high-order 6 bits) INTT0 start address (low-order 8 bits) Branch addresses for the following instructions * BR BCDE * BR BCXA * BR !addr * CALL !addr Branch/call address by GETI 000CH MBE RBE INTT1, INTT2 start address (high-order 6 bits) INTT1, INTT2 start address (low-order 8 bits) 0020H Reference table for GETI instruction 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH BR $addr instruction relative branch address (-15 to -1, +2 to +16) BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch to addresses with changes in the PC's low-order 8 bits only. Data Sheet U11917EJ2V0DS00 17 PD75P3018A Figure 6-3. Program Memory Map (Mk II mode) 7 0000H MBE 6 RBE 5 0 Internal reset start address (high-order 6 bits) Internal reset start address (low-order 8 bits) 0002H MBE RBE INTBT/INT4 start address (high-order 6 bits) INTBT/INT4 start address (low-order 8 bits) 0004H MBE RBE INT0 start address (high-order 6 bits) INT0 start address (low-order 8 bits) 0006H MBE RBE INT1 start address (high-order 6 bits) INT1 start address (low-order 8 bits) 0008H MBE RBE INTCSI start address (high-order 6 bits) INTCSI start address (low-order 8 bits) 000AH MBE RBE INTT0 start address (high-order 6 bits) INTT0 start address (low-order 8 bits) 000CH MBE RBE INTT1, INTT2 start address (high-order 6 bits) INTT1, INTT2 start address (low-order 8 bits) BRCB !caddr instruction branch address CALLF !faddr instruction entry address Branch addresses for the following instructions * BR BCDE * BR BCXA * BRA !addr1 * CALLA !addr1 BR $addr1 instruction relative branch address (-15 to -1, +2 to +16) 0020H Reference table for GETI instruction 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH 4000H 4FFFH 5000H 5FFFH 6000H 6FFFH 7000H 7FFFH BR !addr instruction branch address CALL !addr instruction branch address Branch/call address by GETI BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address Caution To allow the vectored interrupt's 14-bit start address (noted above), set the address within a 16K area (0000H to 3FFFH). Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch to addresses with changes in the PC's low-order 8 bits only. Data Sheet U11917EJ2V0DS00 18 PD75P3018A 6.3 Data Memory (RAM) ... 1024 x 4 bits Figure 6-4 shows the data memory configuration. Data memory consists of a data area and a peripheral hardware area. The data area consists of 1024 x 4-bit static RAM. Figure 6-4. Data Memory Map Data memory 000H General-purpose register area 01FH 020H 0 256 x 4 (224 x 4) 0FFH 100H 256 x 4 (224 x 4) 1DFH 1E0H Display data memory 1FFH 200H Data area static RAM (1024 x 4) Stack area Note 256 x 4 2 (32 x 4) 1 (32 x 4) Memory bank 2FFH 300H 256 x 4 3 3FFH Not incorporated F80H Peripheral hardware area 128 x 4 15 FFFH Note Memory bank 0, 1, 2, or 3 can be selected as the stack area. Data Sheet U11917EJ2V0DS00 19 PD75P3018A 7. INSTRUCTION SET (1) Representation and coding formats for operands In the instruction's operand area, use the following coding format to describe operands corresponding to the instruction's operand representations (for further description, see the RA75X Assembler Package User's Manual Language (U12385E)). When there are several codes, select and use just one. Codes that consist of uppercase letters and + or - symbols are key words that should be entered as they are. For immediate data, enter an appropriate numerical value or label. Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (For details, refer to the PD753017 User's Manual (U11282E)). The number of labels that can be entered for fmem and pmem are restricted. Representation reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IEXXX RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-3FFFH immediate data or label 0000H-7FFFH immediate data or label (Mk II mode only) 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (however, bit0 = 0) or label PORT0-PORT7 IEBT, IECSI, IET0, IET1, IET2, IE0-IE2, IE4, IEW RB0-RB3 MB0-MB3, MB15 Coding Format Note When processing 8-bit data, only even-numbered addresses can be specified. 20 Data Sheet U11917EJ2V0DS00 PD75P3018A (2) Operation legend A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE IME IPS IEXXX RBS MBS PCC . (XX) XXH : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : Register pair (XA); 8-bit accumulator : Register pair (BC) : Register pair (DE) : Register pair (HL) : Expansion register pair (XA') : Expansion register pair (BC') : Expansion register pair (DE') : Expansion register pair (HL') : Program counter : Stack pointer : Carry flag; bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Interrupt master enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Delimiter for address and bit : Addressed data : Hexadecimal data PORTn : Port n (n = 0 to 7) Data Sheet U11917EJ2V0DS00 21 PD75P3018A (3) Description of symbols used in addressing area MB = MBE * MBS *1 MBS = 0-3, 15 *2 *3 MB = 0 MBE = 0 : MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) MBE = 1 : MB = MBS MBS = 0-3, 15 *4 *5 *6 *7 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr = 0000H-3FFFH addr, addr1 = (Current PC) -15 to (Current PC) -1 (Current PC) +2 to (Current PC) +16 *8 caddr = 0000H-0FFFH (PC14, 13, 12 = 000B) or 1000H-1FFFH (PC14, 13, 12 = 001B) or 2000H-2FFFH (PC14, 13, 12 = 010B) or 3000H-3FFFH (PC14, 13, 12 = 011B) or 4000H-4FFFH (PC14, 13, 12 = 100B: Mk II mode only) or 5000H-5FFFH (PC14, 13, 12 = 101B: Mk II mode only) or 6000H-6FFFH (PC14, 13, 12 = 110B: Mk II mode only) or 7000H-7F7FH (PC14, 13, 12 = 111B: Mk II mode only) *9 *10 *11 faddr = 0000H-07FFH taddr = 0020H-007FH addr1 = 0000H-7FFFH (Mk II mode only) Program memory addressing Data memory addressing Remarks 1. MB indicates access-enabled memory banks. 2. In area *2, MB = 0 for both MBE and MBS. 3. In areas *4 and *5, MB = 15 for both MBE and MBS. 4. Areas *6 to *11 indicate corresponding address-enabled areas. 22 Data Sheet U11917EJ2V0DS00 PD75P3018A (4) Description of machine cycles S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as shown below. * No skip ..................................................................... S = 0 * Skipped instruction is 1-byte or 2-byte instruction .... S = 1 * Skipped instruction is 3-byte instructionNote .............. S = 2 Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1 Caution The GETI instruction is skipped for one machine cycle. One machine cycle equals one cycle (= tCY) of the CPU clock . Use the PCC setting to select among four cycle times. Data Sheet U11917EJ2V0DS00 23 PD75P3018A Instruction Group Transfer Mnemonic MOV Operand A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA No. of Machine Bytes Cycle 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) Operation Addressing Area Skip Condition String-effect A String-effect A String-effect B *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L=FH A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' XA (PC13-8+DE)ROM XA (PC14-8+DE)ROM XCH A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp' *1 *1 *1 *2 *1 *3 *3 L=0 L=FH Table reference MOVTNote 1 XA, @PCDE XA, @PCXA 1 3 XA (PC13-8+XA)ROM XA (PC14-8+XA)ROM XA, @BCDE 1 3 XA (BCDE)ROMNote 2 XA (BCDE)ROM Note 2 *6 *11 *6 *11 XA, @BCXA 1 3 XA (BCXA)ROM XA (BCXA)ROM Note 2 Note 2 Notes 1. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only. 2. Only the low-order 3 bits in the B register are valid. 24 Data Sheet U11917EJ2V0DS00 PD75P3018A Instruction Group Bit transfer Mnemonic MOV1 Operand CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY No. of Machine Bytes Cycle 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S Operation CY (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) CY A A+n4 XA XA+n8 A A+(HL) XA XA+rp' rp'1 rp'1+XA A, CY A+(HL)+CY XA, CY XA+rp'+CY rp'1, CY rp'1+XA+CY A A-(HL) XA XA-rp' rp'1 rp'1-XA A, CY A-(HL)-CY XA, CY XA-rp'-CY rp'1, CY rp'1-XA-CY AA AA n4 (HL) Addressing Area *4 *5 *1 *4 *5 *1 Skip Condition Arithmetic ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA carry carry *1 carry carry carry *1 ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA *1 borrow borrow borrow SUBC A, @HL XA, rp' rp'1, XA *1 AND A, #n4 A, @HL XA, rp' rp'1, XA XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA CY A0, A3 CY, An-1 An AA reg reg+1 rp1 rp1+1 (HL) (HL)+1 (mem) (mem)+1 reg reg-1 rp' rp'-1 *1 *3 reg=0 rp1=00H (HL)=0 (mem)=0 reg=FH rp'=FFH *1 *1 OR A, #n4 A, @HL XA, rp' rp'1, XA XOR A, #n4 A, @HL XA, rp' rp'1, XA Accumulator manipulation Increment/ decrement RORC NOT INCS A A reg rp1 @HL mem DECS reg rp' Data Sheet U11917EJ2V0DS00 *1 25 PD75P3018A Instruction Group Comparison Mnemonic SKE Operand reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' No. of Machine Bytes Cycle 2 2 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 Skip if reg=n4 Skip if (HL)=n4 Skip if A=(HL) Operation Addressing Area Skip Condition reg=n4 *1 *1 *1 (HL)=n4 A=(HL) XA=(HL) A=reg XA=rp' Skip if XA=(HL) Skip if A=reg Skip if XA=rp' CY 1 CY 0 Skip if CY=1 CY CY (mem.bit) 1 (fmem.bit) 1 (pmem7-2+L3-2.bit(L1-0)) 1 (H+mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2+L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if(mem.bit)=1 Skip if(fmem.bit)=1 Skip if(pmem7-2+L3-2.bit(L1-0))=1 Skip if(H+mem3-0.bit)=1 Skip if(mem.bit)=0 Skip if(fmem.bit)=0 Skip if(pmem7-2+L3-2.bit(L1-0))=0 Skip if(H+mem3-0.bit)=0 Skip if(fmem.bit)=1 and clear Skip if(pmem7-2+L3-2.bit (L1-0))=1 and clear Skip if(H+mem3-0.bit)=1 and clear CY CY (fmem.bit) Carry flag manipulation SET1 CLR1 SKT NOT1 CY CY CY CY mem.bit fmem.bit pmem.@L @H+mem.bit CY=1 Memory bit manipulation SET1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 (mem.bit)=1 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@L)=0 (@H+mem.bit)=0 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 CLR1 mem.bit fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit SKF mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit CY CY (pmem7-2+L3-2.bit(L1-0)) CY C (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY C (H+mem3-0.bit) OR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit XOR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit 26 Data Sheet U11917EJ2V0DS00 PD75P3018A Instruction Group Branch Mnemonic BRNote 1 Operand addr No. of Machine Bytes Cycle -- -- Operation PC14 0, PC13-0 addr Use the assembler to select the most appropriate instruction among the following. * BR !addr * BRCB !caddr * BR $addr PC14-0 addr1 Use the assembler to select the most appropriate instruction among the following. * BRA !addr1 * BR !addr * BRCB !caddr * BR $addr1 PC14 0, PC13-0 addr PC14 0, PC13-0 addr PC14-0 addr1 PC14 0, PC13-0 PC13-8+DE PC14-0 PC14-8+DE Addressing Area *6 Skip Condition addr1 -- -- *11 !addr $addr $addr1 PCDE 3 1 1 2 3 2 2 3 *6 *7 PCXA 2 3 PC14 0, PC13-0 PC13-8+XA PC14-0 PC14-8+XA BCDE 2 3 PC14 0, PC13-0 BCDENote 2 PC14-0 BCDE Note 2 Note 2 *6 *11 *6 *11 *6 *11 *8 BCXA 2 3 PC14 0, PC13-0 BCXA PC14-0 BCXA Note 2 BRA Note 1 !addr 3 3 3 3 2 PC14 0, PC13-0 addr PC14-0 addr1 PC14 0, PC13-0 PC13, 12+caddr11-0 PC14-0 PC14, 13, 12+caddr11-0 BRCB Note 1 !caddr 2 Notes 1. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only. 2. The only following bits are valid in the B register. For Mk I mode : Low-order 2 bits For Mk II mode : Low-order 3 bits Data Sheet U11917EJ2V0DS00 27 PD75P3018A Instruction Group Subroutine stack control Mnemonic CALLANote Operand !addr1 No. of Machine Bytes Cycle 3 3 Operation (SP-5) 0, PC14-12 (SP-6)(SP-3)(SP-4) PC11-0 (SP-2) X, X, MBE, RBE PC14-0 addr1, SP SP-6 Addressing Area *11 Skip Condition CALL Note !addr 3 3 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, 12 PC14 0, PC13-0 addr, SP SP-4 *6 4 (SP-5) 0, PC14-12 (SP-6)(SP-3)(SP-4) PC11-0 (SP-2) X, X, MBE, RBE PC14 0, PC13-0 addr, SP SP-6 CALLFNote !faddr 2 2 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, 12 PC14 0, PC13-0 000+faddr, SP SP-4 *9 3 (SP-5) 0, PC14-12 (SP-6)(SP-3)(SP-4) PC11-0 (SP-2) X, X, MBE, RBE PC14-0 0000+faddr, SP SP-6 RET Note 1 3 MBE, RBE, PC13, 12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PC14 0, SP SP+4 X, X, MBE, RBE (SP+4) 0, PC14-12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+6 RETS Note 1 3+S MBE, RBE, PC13, 12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PC14 0, SP SP+4 then skip unconditionally X, X, MBE, RBE (SP+4) 0, PC14-12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+6 then skip unconditionally Unconditional RETINote 1 3 MBE, RBE, PC13, 12 (SP+1), PC14 0 PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 0, PC14-12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 Note Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only. 28 Data Sheet U11917EJ2V0DS00 PD75P3018A Instruction Group Subroutine stack control Mnemonic PUSH rp BS POP rp BS Operand No. of Machine Bytes Cycle 1 2 1 2 2 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 Operation (SP-1)(SP-2) rp, SP SP-2 (SP-1) MBS, (SP-2) RBS, SP SP-2 rp (SP+1)(SP), SP SP+2 MBS (SP+1), RBS (SP), SP SP+2 IME(IPS.3) 1 IEXXX 1 IME(IPS.3) 0 IEXXX 0 A PORTn (n=0-7) Addressing Area Skip Condition Interrupt control EI IEXXX DI IEXXX 2 2 2 2 2 2 2 2 2 1 I/O IN Note 1 A, PORTn XA, PORTn XA PORTn+1, PORTn (n=4, 6) PORTn A (n=2-7) OUTNote 1 PORTn, A PORTn, XA PORTn+1, PORTn XA (n=4, 6) Set HALT Mode(PCC.2 1) Set STOP Mode(PCC.3 1) No Operation RBS n (n=0-3) MBS n (n=0-3, 15) * When using TBR instruction PC13-0 (taddr)5-0+(taddr+1), PC14 0 --------------------------- CPU control HALT STOP NOP Special SEL RBn MBn 2 2 1 GETI Note 2, 3 taddr *10 * When using TCALL instruction (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, 12, PC14 0 PC13-0 (taddr)5-0+(taddr+1) --------------------------- SP SP-4 ------------ * When using instruction other than TBR or TCALL Execute (taddr)(taddr+1) instructions 1 3 * When using TBR instruction PC13-0 (taddr)5-0+(taddr+1), PC14 0 ------- - - - - - - - - - - - - - -- -- -- -- ------- -- -- -- -- - - - - - - -------- Determined by referenced instruction *10 ------------ 4 * When using TCALL instruction (SP-5) 0, PC14-12 (SP-6)(SP-3)(SP-4) PC11-0 (SP-2) X, X, MBE, RBE, PC14 0 PC13-0 (taddr)5-0+(taddr+1) SP SP-6 -------- - - - - - - - - - - - -- -- -- -- ----- -- -- -- -- - - - - - - - - - -------- ------------ 3 * When using instruction other than TBR or TCALL Execute (taddr)(taddr+1) instructions Determined by referenced instruction Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15. 2. TBR and TCALL instructions are assembler pseudo-instructions for the GETI instruction's table definitions. 3. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only. Data Sheet U11917EJ2V0DS00 29 PD75P3018A 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY The program memory contained in the PD75P3018A is a 32768 x 8-bit one-time PROM that can be electrically written one time only. The pins listed in the table below are used for this one-time PROM's write/verify operations. Clock input from the X1 pin is used instead of address input as a method for updating addresses. Pin VPP X1, X2 Function Pin where program voltage is applied during program memory write/verify (usually VDD potential) Clock input pins for address updating during program memory write/verify. Input the X1 pin's inverted signal to the X2 pin. Operation mode selection pin for program memory write/verify 8-bit data I/O pins for program memory write/verify MD0-MD3 D0/P40 to D3/P43 (low-order 4 bits) D4/P50 to D7/P53 (high-order 4 bits) VDD Pin where power supply voltage is applied. Applies VDD = 1.8 to 5.5 V in normal operation mode and +6 V for program memory write/verify. Caution Pins not used for program memory write/verify should be connected to VSS via a resistor individually. 8.1 Operation Modes for Program Memory Write/Verify When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the PD75P3018A enters the program memory write/verify mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below. Operation Mode Specification VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L X MD2 H H H H MD3 L H H H Zero-clear program memory address Write mode Verify mode Program inhibit mode Operation Mode X: L or H 30 Data Sheet U11917EJ2V0DS00 PD75P3018A 8.2 Program Memory Write Procedure Program memory can be written at high speed using the following procedure. (1) Pull unused pins to Vss through resistors. Set the X1 pin low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait 10 s. (4) Select the zero-clear program memory address mode. (5) Supply 6 V to the VDD and 12.5 V to the VPP pins. (6) Write data in the 1 ms write mode. (7) Select the verify mode. If the data is correct, go to step (8) and if not, repeat steps (6) and (7). (8) (X : number of write operations from steps (6) and (7)) x 1 ms additional write. (9) Apply four pulses to the X1 pin to increment the program memory address by one. (10) Repeat steps (6) to (9) until the end address is reached. (11) Select the zero-clear program memory address mode. (12) Return the VDD and VPP pins back to 5 V. (13) Turn off the power. The following figure shows steps (2) to (9). X repetitions Write VPP VDD VDD + 1 VDD VDD Verify Additional write Address increment VPP X1 D0/P40 to D3/P43 D4/P50 to D7/P53 Data input Data output Data input MD0/P30 MD1/P31 MD2/P32 MD3/P33 Data Sheet U11917EJ2V0DS00 31 PD75P3018A 8.3 Program Memory Read Procedure The PD75P3018A can read program memory contents using the following procedure. (1) Pull unused pins to Vss through resistors. Set the X1 pin low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait 10 s. (4) Select the zero-clear program memory address mode. (5) Supply 6 V to the VDD and 12.5 V to the VPP pins. (6) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one address. (7) Select the zero-clear program memory address mode. (8) Return the VDD and VPP pins back to 5 V. (9) Turn off the power. The following figure shows steps (2) to (7). VPP VPP VDD VDD + 1 VDD VDD X1 D0/P40 to D3/P43 D4/P50 to D7/P53 Data output Data output MD0/P30 MD1/P31 "L" MD2/P32 MD3/P33 32 Data Sheet U11917EJ2V0DS00 PD75P3018A 8.4 One-time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends that after the required data is written and the PROM is stored under the temperature and time conditions shown below, the PROM should be verified via a screening. Storage Temperature 125C Storage Time 24 hours Data Sheet U11917EJ2V0DS00 33 PD75P3018A 9. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage PROM supply voltage Input voltage Symbol VDD VPP VI1 VI2 Output voltage High-level output current VO IOH Per pin Total of all pins Low-level output current IOL Per pin Total of all pins Operating ambient temperature Storage temperature TA Tstg Other than ports 4 and 5 Ports 4 and 5 (During N-ch open drain) Conditions Ratings -0.3 to +7.0 -0.3 to +13.5 -0.3 to VDD + 0.3 -0.3 to +14 -0.3 to VDD + 0.3 -10 -30 30 220 -40 to +85Note -65 to +150 Unit V V V V V mA mA mA mA C C Note To drive LCD in normal mode, TA = -10 to +85C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Capacitance (TA = 25C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF 34 Data Sheet U11917EJ2V0DS00 PD75P3018A Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Ceramic resonator X1 X2 Recommended Circuit Parameter Oscillation frequency (fX)Note 1 Conditions MIN. 1.0 TYP. MAX. 6.0Note 2 Unit MHz C1 VDD C2 Oscillation stabilization timeNote 3 After VDD has reached MIN. value of oscillation voltage range 1.0 4 ms Crystal resonator X1 X2 Oscillation frequency (fX)Note 1 6.0Note 2 MHz C1 VDD C2 Oscillation stabilization timeNote 3 VDD = 4.5 to 5.5 V 10 30 ms External clock X1 X2 X1 input frequency (fX)Note 1 1.0 6.0Note 2 MHz X1 input high-/ low-level width (tXH, tXL) 83.3 500 ns Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. 2. If the oscillation frequency is 4.19 MHz < fX 6.0 MHz at 1.8 V VDD < 2.7 V, do not select processor clock control register (PCC) = 0011. If PCC = 0011, one machine cycle is less than 0.95 s, falling short of the rated value of 0.95 s. 3. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied or STOP mode has been released. Caution When using the main system clock oscillator, wire the portion enclosed in the broken line in the above figure as follows to prevent adverse influence due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator at the same potential as VDD. * Do not ground to a power supply pattern through which a high current flows. * Do not extract signals from the oscillator. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U11917EJ2V0DS00 35 PD75P3018A Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Crystal resonator XT1 XT2 R C3 VDD C4 Recommended Circuit Parameter Oscillation frequency (fXT)Note 1 Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz Oscillation stabilization timeNote 2 VDD = 4.5 to 5.5 V 1.0 2 10 s External clock XT1 input frequency (fXT)Note 1 32 100 kHz XT1 XT2 XT1 input high-/ low-level width (tXTH, tXTL) 5 15 s Notes 1. The oscillation frequency and XT1 input frequency shown above indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. 2. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied. Caution When using the subsystem clock oscillator , wire the portion enclosed in the broken line in the above figure as follows to prevent adverse influence due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator at the same potential as VDD. * Do not ground to a power supply pattern through which a high current flows. * Do not extract signals from the oscillator. The subsystem clock oscillator has a low amplification factor to reduce current consumption and is more susceptible to noise than the main system clock oscillator. Therefore, exercise utmost care in wiring the subsystem clock oscillator. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 36 Data Sheet U11917EJ2V0DS00 PD75P3018A DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Low-level output current High-level input voltage VIH2 Ports 0, 1, 6, 7, RESET VIH1 Symbol IOL Per pin Total of all pins Ports 2, 3 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V VIH3 Ports 4, 5 (N-ch open-drain) VIH4 Low-level input voltage VIL2 Ports 0, 1, 6, 7, RESET VIL1 X1, XT1 Ports 2 to 5 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V VIL3 High-level output voltage Low-level output voltage VOL1 VOH X1, XT1 SCK, SO, Ports 2, 3, 6, 7, BP0 to BP7 IOH = -1.0 mA SCK, SO, Ports 2 to 7, BP0 to BP7 IOL = 15 mA VDD = 4.5 to 5.5 V IOL = 1.6 mA VOL2 SB0, SB1 N-ch open-drain Pull-up resistor 1 k High-level input leakage current ILIH1 ILIH2 ILIH3 Low-level input leakage current ILIL1 ILIL2 ILIL3 VIN = 13 V VIN = 0 V VIN = VDD Pins other than X1, XT1 X1, XT1 Ports 4, 5 (N-ch open-drain) Pins other than X1, XT1, Ports 4, 5 X1, XT1 Ports 4, 5 (N-ch open-drain) When input instruction is not executed Ports 4, 5 (N-ch opendrain). When input instruction is executed High-level output leakage current Low-level output leakage current Internal pull-up resistor RL VIN = 0 V Ports 0 to 3, 6, 7 (except P00 pin) 50 100 200 k ILOH1 ILOH2 ILOL VOUT = VDD VOUT = 13 V VOUT = 0 V VDD = 5.0 V VDD = 3.0 V -10 -3 -30 -27 -8 3 20 -3 3 20 20 -3 -20 -3 0.4 0.2VDD V V 0.2 2.0 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 0.7VDD 0.9VDD 0.8VDD 0.9VDD 0.7VDD 0.9VDD VDD - 0.1 0 0 0 0 0 VDD - 0.5 Conditions MIN. TYP. MAX. 15 150 VDD VDD VDD VDD 13 13 VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD 0.1 Unit mA mA V V V V V V V V V V V V V A A A A A A A A A A A A SCK, SO/SB0, SB1, Ports 2, 3, 6, 7 Ports 4, 5 (N-ch open-drain) Data Sheet U11917EJ2V0DS00 37 PD75P3018A DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Symbol VAC0 = 0 Conditions TA = -40 to +85C TA = -10 to +85C VAC0 = 1 VAC current Note 1 MIN. 2.7 2.2 1.8 TYP. MAX. VDD VDD VDD Unit V V V LCD drive voltage VLCD IVAC VAC0 = 1, VDD = 2.0 V 10% IO = 1.0 A VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 IO = 0.5 A 1.8 V VLCD VDD 0 0 1 4 0.2 A V LCD output voltage VODC deviation Note 2 (common) LCD output voltage VODS deviation Note 2 0.2 V (segment) Supply currentNote 3 IDD1 6.0 MHzNote 4 VDD = 5.0 V 10%Note 5 crystal IDD2 oscillation VDD = 3.0 V 10%Note 6 HALT VDD = 5.0 V 10% VDD = 3.0 V 10% Note 5 Note 6 3.7 0.73 0.92 0.3 2.7 0.57 0.90 0.28 42 37 42 39 39 8.5 5.8 8.5 3.5 3.5 0.05 0.02 TA = 25C 0.02 11.0 2.2 2.6 0.9 8.0 1.7 2.5 0.8 126 110 84 117 78 25 17 17 12 7 10 5 3 mA mA mA mA mA mA mA mA C1 = C2 = 22 pF mode IDD1 4.19 MHz crystal IDD2 oscillation Note 4 VDD = 5.0 V 10% VDD = 3.0 V 10% HALT VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 3.0 V 10% C1 = C2 = 22 pF mode IDD3 32.768 kHz Note 7 Low- A A A A A A A A A A A A A voltage VDD = 2.0 V 10% mode Note 8 crystal oscillation VDD = 3.0 V, TA = 25C Low current VDD = 3.0 V 10% consumption VDD = 3.0 V, TA = 25C modeNote 9 HALT Lowmode VDD = 3.0 V 10% IDD4 voltage VDD = 2.0 V 10% mode Note 8 VDD = 3.0 V, TA = 25C Low current VDD = 3.0 V 10% consumption VDD = 3.0 V, TA = 25C modeNote 9 IDD5 XT1 = 0 VNote 10 VDD = 5.0 V 10% STOP mode VDD = 3.0 V 10% Notes 1. Clear VAC0 to 0 in the low current consumption mode and STOP mode. When VAC0 is set to 1, the current increases by about 1 A. 2. Voltage deviation is the difference between the ideal values (VLCDn ; n = 0, 1, 2) of the segment and common outputs and the output voltage. 3. The current flowing through the internal pull-up resistor is not included. 4. Including the case when the subsystem clock oscillates. 5. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. 6. When the device operates in low-speed mode with PCC set to 0000. 7. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. 8. When the sub-oscillation circuit control register (SOS) is set to 0000. 9. When the SOS is set to 0010. 10. When the SOS is set to 00x1, and the feedback resistor of the sub-oscillator is cut (x: don't care). 38 Data Sheet U11917EJ2V0DS00 PD75P3018A AC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter CPU clock cycle time Note 1 (minimum instruction execution time = 1 machine cycle) TI0, TI1, TI2 input frequency fTI Symbol tCY Operation with main system clock Operation with subsystem clock VDD = 2.7 to 5.5 V Conditions VDD = 2.7 to 5.5 V MIN. 0.67 0.95 114 0 0 TI0, TI1, TI2 input high-/ low-level width Interrupt input high-/low-level tINTH, tINTL INT0 width INT1, 2, 4 KR0-7 RESET low-level width tRSL IM02 = 0 IM02 = 1 tTIH, tTIL VDD = 2.7 to 5.5 V 0.48 1.8 Note 2 10 10 10 10 122 TYP. MAX. 64 64 125 1.0 275 Unit s s s MHz kHz s s s s s s s Notes 1. The cycle time (minimum instruction execution time) of the CPU clock () is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC), and processor clock control register (PCC). Cycle time tCY [s] 64 60 6 5 4 3 Operation guaranteed range tCY vs VDD (with main system clock) The figure on the right shows the supply voltage VDD vs. cycle time tCY characteristics when the device operates with the main system clock. 2. 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0). 2 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] Data Sheet U11917EJ2V0DS00 39 PD75P3018A Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK ... internal clock output): (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-/low-level width tKL1, tKH1 VDD = 2.7 to 5.5 V tKCY1/2-50 tKCY1/2-150 SI Note 1 TYP. MAX. Unit ns ns ns ns ns ns ns ns setup time (to SCK ) tSIK1 VDD = 2.7 to 5.5 V 150 500 SI Note 1 hold time (from SCK ) tKSI1 VDD = 2.7 to 5.5 V 400 600 SCK SO delay time Note 1 output tKSO1 RL = 1 k, Note 2 VDD = 2.7 to 5.5 V 0 0 250 1000 ns ns CL = 100 pF Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead. 2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line. 2-wire and 3-wire serial I/O modes (SCK ... external clock input): (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-/low-level width tKL2, tKH2 VDD = 2.7 to 5.5 V 400 1600 SI Note 1 TYP. MAX. Unit ns ns ns ns ns ns ns ns setup time (to SCK ) tSIK2 VDD = 2.7 to 5.5 V 100 150 SINote 1 hold time (from SCK ) tKSI2 VDD = 2.7 to 5.5 V 400 600 SCK SONote 1 output delay time tKSO2 RL = 1 k, Note 2 CL = 100 pF VDD = 2.7 to 5.5 V 0 0 300 1000 ns ns Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead. 2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line. 40 Data Sheet U11917EJ2V0DS00 PD75P3018A SBI mode (SCK ... internal clock output (master)): (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY3 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-/low-level width tKL3, tKH3 VDD = 2.7 to 5.5 V tKCY3/2-50 tKCY3/2-150 SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) tKSI3 SCK SB0, 1 output delay time SCK SB0, 1 SB0, 1 SCK SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSO3 RL = 1 k, Note TYP. MAX. Unit ns ns ns ns ns ns ns tSIK3 VDD = 2.7 to 5.5 V 150 500 tKCY3/2 VDD = 2.7 to 5.5 V 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 ns ns ns ns ns ns CL = 100 pF Note RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line. SBI mode (SCK ... external clock input (slave)): (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY4 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-/low-level width tKL4, tKH4 VDD = 2.7 to 5.5 V 400 1600 SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) tKSI4 SCK SB0, 1 output delay time SCK SB0, 1 SB0, 1 SCK SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSO4 RL = 1 k, Note TYP. MAX. Unit ns ns ns ns ns ns ns tSIK4 VDD = 2.7 to 5.5 V 100 150 tKCY4/2 VDD = 2.7 to 5.5 V 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000 ns ns ns ns ns ns CL = 100 pF Note RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line. Data Sheet U11917EJ2V0DS00 41 PD75P3018A AC Timing Test Points (except X1 and XT1 inputs) VIH (MIN.) VIL (MAX.) VIH (MIN.) VIL (MAX.) VOH (MIN.) VOL (MAX.) VOH (MIN.) VOL (MAX.) Clock Timing 1/fX tXL tXH VDD-0.1 V X1 input 0.1 V 1/fXT tXTL tXTH VDD-0.1 V XT1 input 0.1 V TI0, TI1, TI2 Timing 1/fTI tTIL tTIH TI0, TI1, TI2 42 Data Sheet U11917EJ2V0DS00 PD75P3018A Serial Transfer Timing 3-wire Serial I/O Mode tKCY1,2 tKL1,2 tKH1,2 SCK tSIK1,2 tKSI1,2 SI Input data tKSO1,2 SO Output data 2-wire Serial I/O Mode tKCY1,2 tKL1,2 tKH1,2 SCK tSIK1,2 tKSI1,2 SB0, 1 tKSO1,2 Data Sheet U11917EJ2V0DS00 43 PD75P3018A Serial Transfer Timing Bus Release Signal Transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 SB0, 1 tKSO3, 4 Command Signal Transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSBK tSIK3, 4 tKSI3, 4 SB0, 1 tKSO3, 4 Interrupt Input Timing tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET Input Timing tRSL RESET 44 Data Sheet U11917EJ2V0DS00 PD75P3018A Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = -40 to +85C) Parameter Data retention power supply voltage Release signal setup time Oscillation stabilization wait timeNote 1 tSREL tWAIT Released by RESET Released by interrupt request 0 2 /fX Note 2 15 Symbol VDDDR Conditions MIN. 1.8 TYP. MAX. 5.5 Unit V s ms ms Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. 2. Set by the basic interval timer mode register (BTM). (Refer to the table below.) Wait Time BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 fX = 4.19 MHz 0 1 1 1 20 20 fX = 6.0 MHz 2 /fX (approx. 250 ms) 2 /fX (approx. 175 ms) 217/fX (approx. 31.3 ms) 217/fX (approx. 21.8 ms) 215/fX (approx. 7.81 ms) 215/fX (approx. 5.46 ms) 213/fX (approx. 1.95 ms) 213/fX (approx. 1.37 ms) Data Retention Timing (when STOP mode released by RESET) Internal reset operation HALT mode STOP mode Data retention mode Operation mode VDD VDDDR STOP instruction execution tSREL RESET tWAIT Data Retention Timing (standby release signal: when STOP mode released by interrupt signal) HALT mode STOP mode Data retention mode Operation mode VDD VDDDR STOP instruction execution tSREL Standby release signal (interrupt request) tWAIT Data Sheet U11917EJ2V0DS00 45 PD75P3018A DC Programming Characteristics (TA = 25 5C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) Parameter High-level input voltage Symbol VIH1 VIH2 Low-level input voltage VIL1 VIL2 Input leakage current High-level output voltage Low-level output voltage VDD supply current VPP supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Conditions Pins other than X1, X2 X1, X2 Pins other than X1, X2 X1, X2 VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD - 1.0 0.4 30 30 MIN. 0.7VDD VDD - 0.5 0 0 TYP. MAX. VDD VDD 0.3VDD 0.4 10 Unit V V V V A V V mA mA Cautions 1. Ensure that VPP does not exceed +13.5 V including overshoot. 2. VDD must be applied before VPP, and cut after VPP. AC Programming Characteristics (TA = 25 5C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) Parameter Address setup time Note 2 Symbol (to MD0) tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tM0S tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR Note 2 Note 1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR -- -- -- -- -- -- -- tACC tOH -- -- Conditions MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2 TYP. MAX. Unit s s s s s 130 ns MD1 setup time (to MD0) Data setup time (to MD0) Address hold time Note 2 (from MD0) Data hold time (from MD0) MD0Data output float delay time VPP setup time (to MD3) VDD setup time (to MD3) Initial program pulse width Additional program pulse width MD0 setup time (to MD1) MD0Data output delay time MD1 hold time (from MD0) MD1 recovery time (from MD0) Program counter reset time X1 input high-/low-level widths X1 input frequency Initial mode setting time MD3 setup time (to MD1) MD3 hold time (from MD1) MD3 setup time (to MD0) Data output delay time from address Data output hold time from address MD3 hold time (from MD0) MD3Data output float delay time s s 1.0 1.05 21.0 ms ms s 1 MD0 = MD1 = VIL tM1H + tM1R 50 s 2 2 10 0.125 s s s s s 4.19 2 2 2 Program memory read Program memory read Program memory read Program memory read Program memory read 0 2 2 2 2 130 MHz s s s s s s s s tDAD tHAD tM3HR tDFR Note 2 Notes 1. Symbol of corresponding PD27C256A 2. The internal address signal is incremented by 1 on the 4th rise of the X1 input, and is not connected to a pin. 46 Data Sheet U11917EJ2V0DS00 PD75P3018A Program Memory Write Timing tVPS VPP VPP VDD tVDS VDD+1 VDD VDD X1 tXL Data Input tI MD0/P30 tPW MD1/P31 tPCR MD2/P32 tM3S MD3/P33 tM3H tM1S tM1H tM1R tM0S tOPW tDS tDH tDV tDF Data Output Data Input tDS tDH tAH tAS Data Input tXH D0/P40-D3/P43 D4/P50-D7/P53 Program Memory Read Timing tVPS VPP VPP VDD tVDS VDD+1 VDD VDD X1 tXL tHAD D0/P40-D3/P43 D4/P50-D7/P53 tI MD0/P30 tDV tM3HR Data Output Data Output tDFR tDAD tXH MD1/P31 tPCR MD2/P32 tM3SR MD3/P33 Data Sheet U11917EJ2V0DS00 47 PD75P3018A 10. PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end S CD Q R 80 1 21 20 F G H I M J P K S N S L M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.20.4 14.00.2 14.00.2 17.20.4 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX. S80GC-65-3B9-6 48 Data Sheet U11917EJ2V0DS00 PD75P3018A 80-PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end S C D R Q 80 1 21 20 F J G P H I M K S N S L M ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 3 +7 -3 1.70 MAX. P80GC-65-8BT-1 NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. Data Sheet U11917EJ2V0DS00 49 PD75P3018A 80 PIN PLASTIC TQFP (FINE PITCH) (12x12) A B 60 61 41 40 detail of lead end S C D Q R 80 1 20 21 F G P H I M J K M N NOTE S L S ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.000.20 12.000.20 12.000.20 14.000.20 1.25 1.25 0.22 +0.05 -0.04 0.10 0.50 (T.P.) 1.000.20 0.500.20 0.145 +0.055 -0.045 0.10 1.050.07 0.100.05 55 1.27 MAX. P80GK-50-BE9-6 Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 50 Data Sheet U11917EJ2V0DS00 PD75P3018A 80-PIN PLASTIC TQFP (FINE PITCH) (12x12) A B 60 61 41 40 detail of lead end S C D P T 80 1 F G H I M 21 20 Q J R L U K S N NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. S M ITEM A B C D F G H I J K L M N P Q R S T U MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.1450.05 0.08 1.0 0.10.05 3 +4 -3 1.10.1 0.25 0.60.15 P80GK-50-9EU-1 Data Sheet U11917EJ2V0DS00 51 PD75P3018A 11. RECOMMENDED SOLDERING CONDITIONS Solder the PD75P3018A under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 11-1. Soldering Conditions of Surface Mount Type (1/2) (1) PD75P3018AGC-3B9: 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) Soldering Method Infrared reflow VPS Wave soldering Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds or below (210C or higher), Number of reflow processes: 3 max. Package peak temperature: 215C, Reflow time: 40 seconds or below (200C or higher), Number of reflow processes: 3 max. Solder temperature: 260C or below, Flow time: 10 seconds or below, Number of flow processes: 1 Preheating temperature: 120C or below (package surface temperature) Pin temperature: 300C or below, Time: 3 seconds or below (per side of device) Symbol IR35-00-3 VP15-00-3 WS60-00-1 Partial heating -- Caution Do not use two or more soldering methods in combination (except the partial heating method). (2) PD75P3018AGC-8BT: 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) Soldering Method Infrared reflow VPS Wave soldering Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds or below (210C or higher), Number of reflow processes: 2 max. Package peak temperature: 215C, Reflow time: 40 seconds or below (200C or higher), Number of reflow processes: 2 max. Solder temperature: 260C or below, Flow time: 10 seconds or below, Number of flow processes: 1 Preheating temperature: 120C or below (package surface temperature) Pin temperature: 300C or below, Time: 3 seconds or below (per side of device) Symbol IR35-00-2 VP15-00-2 WS60-00-1 Partial heating -- Caution Do not use two or more soldering methods in combination (except the partial heating method). 52 Data Sheet U11917EJ2V0DS00 PD75P3018A Table 11-1. Soldering Conditions of Surface Mount Type (2/2) (3) PD75P3018AGK-BE9: 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.05 mm) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds or below (210C or higher), Number of reflow processes: 3 max., Exposure limit: 7 daysNote (After that, prebaking is necessary at 125C for 10 hours) Package peak temperature: 215C, Reflow time: 40 seconds or below (200C or higher), Number of reflow processes: 3 max., Exposure limit: 7 daysNote (After that, prebaking is necessary at 125C for 10 hours) Pin temperature: 300C or below, Time: 3 seconds or below (per side of device) Symbol IR35-107-3 VPS VP15-107-3 Partial heating -- Note The number of days for storage after the dry pack has been opened. The storage conditions are 25C, 65% RH max. Caution Do not use two or more soldering methods in combination (except the partial heating method). (4) PD75P3018AGK-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.00 mm) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds or below (210C or higher), Number of reflow processes: 2 max., Exposure limit: 7 daysNote (After that, prebaking is necessary at 125C for 10 hours) Package peak temperature: 215C, Reflow time: 40 seconds or below (200C or higher), Number of reflow processes: 2 max., Exposure limit: 7 daysNote (After that, prebaking is necessary at 125C for 10 hours) Pin temperature: 300C or below, Time: 3 seconds or below (per side of device) Symbol IR35-107-2 VPS VP15-107-2 Partial heating -- Note The number of days for storage after the dry pack has been opened. The storage conditions are 25C, 65% RH max. Caution Do not use two or more soldering methods in combination (except the partial heating method). Data Sheet U11917EJ2V0DS00 53 PD75P3018A APPENDIX A. PD75316B, 753017A AND 75P3018A FUNCTION LIST Parameter Program memory PD75316B Mask ROM 0000H-3F7FH (16256 x 8 bits) 000H-3FFH (1024 x 4 bits) 75X Standard PD753017A Mask ROM 0000H-5FFFH (24576 x 8 bits) PD75P3018A One-time PROM 0000H-7FFFH (32768 x 8 bits) Data memory CPU Instruction execution time When main system clock is selected When subsystem clock is selected Pin connection 29 to 32 34 to 37 44 47 48 50 to 53 57 Stack SBS register Stack area Subroutine call instruction stack operation Instruction BRA !addr1 CALLA !addr1 MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA CALL !addr CALLF !faddr Mask option Timer 75XL CPU * 0.95, 1.91, 3.81, or 15.3 s (at 4.19 MHz operation) * 0.67, 1.33, 2.67, or 10.7 s (at 6.0 MHz operation) 0.95, 1.91, or 15.3 s (at 4.19 MHz operation) 122 s (at 32.768 kHz operation) P40 to P43 P50 to P53 P12/INT2 P21 P22/PCL P30 to P33 IC None 000H-0FFH 2-byte stack Unavailable P12/INT2/TI1/TI2 P21/PTO1 P22/PCL/PTO2 P30/MD0 to P33/MD3 VPP SBS.3 = 1; Mk I mode selection SBS.3 = 0; Mk II mode selection n00H-nFFH (n = 0-3) Mk I mode: 2-byte stack Mk II mode: 3-byte stack Mk I mode: unavailable Mk II mode: available Available P40/D0 to P43/D3 P50/D4 to P53/D7 3 machine cycles 2 machine cycles Yes 3 channels: * Basic interval timer : 1 channel * 8-bit timer/event counter : 1 channel * Watch timer: 1 channel Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles None 5 channels: * Basic interval timer/watchdog timer: 1 channel * 8-bit timer/event counter: 3 channels (can be used as 16-bit timer/event counter, carrier generator, timer with gate) * Watch timer: 1 channel 54 Data Sheet U11917EJ2V0DS00 PD75P3018A Parameter Clock output (PCL) PD75316B , 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) 2 kHz (Main system clock: at 4.19 MHz operation) PD753017A PD75P3018A * , 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) * , 750, 375, 93.8 kHz (Main system clock: at 6.0 MHz operation) * 2, 4, 32 kHz (Main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) * 2.93, 5.86, 46.9 kHz (Main system clock: at 6.0 MHz operation) BUZ output (BUZ) Serial interface 3 modes are available * 3-wire serial I/O mode ... MSB/LSB can be selected for transfer first bit * 2-wire serial I/O mode * SBI mode Feedback resistor cut flag (SOS.0) Sub-oscillator current cut flag (SOS.1) None None None Unavailable None External: 3, Internal: 3 VDD = 2.0 to 6.0 V TA = -40 to +85C * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) * 80-pin plastic QFP (14 x 14 mm) Provided Provided Yes Available Yes External: 3, Internal: 5 VDD = 1.8 to 5.5 V SOS register Register bank selection register (RBS) Standby release by INT0 Interrupt priority selection register (IPS) Vectored interrupt Supply voltage Operating ambient temperature Package Data Sheet U11917EJ2V0DS00 55 PD75P3018A APPENDIX B. DEVELOPMENT TOOLS The following development tools have been provided for system development using the PD75P3018A. In the 75XL Series, the relocatable assembler common to series is used in combination with the device file of each type. RA75X relocatable assembler Host machine OS PC-9800 Series MS-DOS TM Part No. (name) Supply medium 3.5" 2HD S5A13RA75X Ver.3.30 to Ver.6.2Note IBM PC/ATTM or compatible Refer to "OS for IBM PCs" 3.5" 2HC S7B13RA75X Device file Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note IBM PC/AT or compatible Refer to "OS for IBM PCs" 3.5" 2HC Supply medium 3.5" 2HD Part No. (name) S5A13DF753017 S7B13DF753017 Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Remark Operation of the assembler and device file is guaranteed only when using the host machine and OS described above. 56 Data Sheet U11917EJ2V0DS00 PD75P3018A PROM Write Tools Hardware PG-1500 This is a PROM programmer that can program single-chip microcontroller with PROM in stand alone mode or under control of host machine when connected with supplied accessory board and optional programmer adapter. It can also program typical PROMs in capacities ranging from 256 K to 4 M bits. This is a PROM programmer adapter for the PD75P3018AGC-3B9. It can be used when connected to a PG-1500. This is a PROM programmer adapter for the PD75P3018AGK-BE9. It can be used when connected to a PG-1500. This is a PROM programmer adapter for the PD75P3018AGC-8BT. It can be used when connected to a PG-1500. This is a PROM programmer adapter for the PD75P3018AGK-9EU. It can be used when connected to a PG-1500. Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500 on host machine. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note IBM PC/AT or compatible Refer to "OS for IBM PCs" 3.5" 2HD Supply medium 3.5" 2HD Part No. (name) PA-75P316BGC PA-75P316BGK PA-75P3018AGC-8BT PA-75P3018AGK-9EU Software PG-1500 controller S5A13PG1500 S7B13PG1500 Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above. Data Sheet U11917EJ2V0DS00 57 PD75P3018A Debugging Tools In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the PD75P3018A. Various system configurations using these in-circuit emulators are listed below. Hardware IE-75000-RNote 1 The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products. For development of the PD75P3018A, the IE-75000-R is used with optional emulation board (IE-75300-R-EM) and emulation probe (EP-753018GC-R or EP-753018GK-R). Highly efficient debugging can be performed when connected to host machine and PROM programmer. The IE-75000-R includes a connected emulation board (IE-75000-R-EM). The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products. The IE-75001-R is used with optional emulation board (IE-75300-R-EM) and emulation probe (EP-753018GC-R or EP-753018GK-R). Highly efficient debugging can be performed when connected to host machine and PROM programmer. This is an emulation board for evaluating application systems using the PD75P3018A. It is used in combination with the IE-75000-R or IE-75001-R. This is an emulation probe for the PD75P3018AGC. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. It includes a 80-pin conversion socket (EV-9200GC-80) to facilitate connections with target system. This is an emulation probe for the PD75P3018AGK. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. IE-75001-R IE-75300-R-EM EP-753018GC-R EV-9200GC-80 EP-753018GK-R TGK-080SDWNote 2 It includes a 80-pin conversion adapter (TGK-080SDW) to facilitate connections with target system. Software IE control program This program can control the IE-75000-R or IE-75001-R on a host machine when connected to the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note 3 IBM PC/AT or compatible Refer to "OS for IBM PCs" Supply medium 3.5" 2HD 5" 2HD 3.5" 2HC 5" 2HC Part No. (name) S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X Notes 1. This is a maintenance product. 2. This is a product of TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics 2nd Department (TEL +81-6-6244-6672) 3. Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Remark Operation of the IE control program is guaranteed only when using the host machine and OS described above. 58 Data Sheet U11917EJ2V0DS00 PD75P3018A OS for IBM PCs The following operating systems for the IBM PC are supported. OS PC DOS TM Version Ver.5.02 to Ver.6.3 J6.1/V to J6.3/V MS-DOS Ver.5.0 to Ver.6.22 5.0/V to 6.2/V IBM DOSTM J5.02/V Caution Ver. 5.0 or later includes a task swapping function, but this software is not able to use that function. Data Sheet U11917EJ2V0DS00 59 PD75P3018A APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device Related Documents Document No. Document Name Japanese English U11662E U11917E (This document) PD753012A, 753016A, 753017A Data Sheet PD75P3018A Data Sheet U11662J U11917J PD753017 User's Manual PD753017 Instruction Table 75XL Series Selection Guide U11282J IEM-5598 U10453J U11282E -- U10453E Development Tool Related Documents Document No. Document Name Japanese Hardware IE-75000-R/IE-75001-R User's Manual IE-75300-R-EM User's Manual EP-753017GC/GK-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual PG-1500 Controller User's Manual Operation Language PC-9800 Series (MS-DOS) base IBM PC Series (PC DOS) base EEU-846 U11354J EEU-967 U11940E U12622J U12385J EEU-704 EEU-5008 English EEU-1416 U11354E EEU-1495 U11940E U12622E U12385E EEU-1291 U10540E Other Related Documents Document No. Document Name Japanese SEMICONDUCTOR SELECTION GUIDE Products & Package (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices Electrostatic Discharge (ESD) Guide to Microcontroller-Related Products by Third Parties C10535J C11531J C10983J C11892J U11416J X13769X C10535E C11531E C10983E C11892E -- English Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents. 60 Data Sheet U11917EJ2V0DS00 PD75P3018A [MEMO] Data Sheet U11917EJ2V0DS00 61 PD75P3018A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 62 Data Sheet U11917EJ2V0DS00 PD75P3018A Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U11917EJ2V0DS00 63 PD75P3018A MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. * The information in this document is current as of May, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 |
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